In recent years, with the fast advancement and development of the semiconductor industry, the semiconductor technology has already been applied in the design and manufacturing of the memory, central processing unit (CPU), liquid crystal display (LCD), light emitting diode (LED), and components or chip sets of other electronic products.
At present, in one aspect, to meet requirements for building a high-speed circuit, strict control needs to be performed on the parasitic capacitance of a pad. Currently, an available technology used to control the capacitance is to use a multilayer clearance area under the pad to reduce the coupling capacitance between the pad and the substrate. In another aspect, to increase exposure precision to increase the integration density of the circuit, an immersion lithography and immersion exposure technology has already been applied in the most advanced semiconductor manufacturing process. The immersion lithography and immersion exposure technology can effectively reduce the exposure size, so that high integration can be achieved.
However, because the whole exposure process needs to be completed in a liquid medium, moisture may be inevitably condensed on the exposed chip. If the condensed moisture cannot be controlled and prevented effectively, the performance of the chip may be greatly affected. Although the multilayer clearance area under the pad can be used to effectively control the parasitic capacitance of the pad, the large area of the multilayer clearance area may hinder the removal of moisture. Therefore, for the conventional low-capacitance pad structure, the chip performance may be affected when moisture cannot be controlled.